1. Field of the Invention
This invention relates to dynamic circuits having improved noise tolerance and methods for designing same. Such dynamic circuits include both combinational and sequential dynamic CMOS logic circuits.
2. Background Art
Dynamic CMOS logic circuits are widely employed in high-performance VLSI chips in pursuing very high system performance. However, dynamic CMOS gates are inherently less resistant to noises than static CMOS gates. With the increasing stringent noise requirement due to aggressive technology scaling, the noise tolerance of dynamic circuits has to be first improved for the overall reliable operation of VLSI chips designed using deep submicron process technology. In the literature, a number of design techniques have been proposed to enhance the noise tolerance of dynamic logic gates.
The following publications are related to this invention, some of which are referenced herein:                [1] P. Larsson et al., “Noise in Digital Dynamic CMOS Circuits,” IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. 29, No. 6, pp. 655–662, June 1994.        [2] K. L. Shepard et al., “Noise in Deep Submicron Digital Design,” in Proc. INTERNATIONAL CONFERENCE ON COMPUTER AIDED DESIGN, pp. 524–531, 1996.        [3] R. H. Krambeck et al., “High-Speed Compact Circuits with CMOS,” IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. SC-17, No. 3, pp. 614–619, June 1982.        [4] V. G. Oklobdziga et al., “Design-Performance Trade-Offs in CMOS Domino Logic,” in Proc. IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE, pp. 334–337, May 1985.        [5] M. H. Anis et al., “High-Speed Dynamic Logic Styles for Scaled-Down CMOS and MTCMOS Technologies,” in Proc. INT. SYMP. LOW POWER ELECTRONICS AND DESIGN, pp. 155–160, 2000.        [6] M. H. Anis et al., “Energy-Efficient Noise Tolerant Dynamic Styles for Scaled-Down CMOS and MTCMOS Technologies,” IEEE TRANSACTIONS ON VLSI SYSTEMS, Vol. 10, No. 2, pp. 71–78, April 2002.        [7] A. Alvandpour et al., “A Conditional Keeper Technique for Sub-0.13μ Wide Dynamic Gates,” in Proc. INT. SYMP. VLSI CIRCUITS, pp. 29–30, 2001.        [8] A. Alvandpour et al., “A Sub-130-nm Conditional Keeper Technique,” IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. 37, No. 5, pp. 633–638, May 2002.        [9] C. M. Lee et al., “Zipper CMOS,” IEEE CIRCUITS AND DEVICES MAGAZINE, Vol. 2, pp. 10–17, May 1986.        [10] J. A. Pretorius et al., “Charge Redistribution and Noise Margins in Domino CMOS Logic,” IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, Vol. CAS-33, No. 8, pp. 786–793, August 1986.        [11] G. P. D'Souza, “Dynamic Logic Circuit with Reduced Charge Leakage,” U.S. Pat. No. 5,483,181, January 1996.        [12] E. B. Schorn, “NMOS Charge-Sharing Prevention Device for Dynamic Logic Circuits,” U.S. Pat. No. 5,838,169, November 1998.        [13] L. Wang et al., “Noise-Tolerant Dynamic Circuit Design,” in Proc. INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, pp. I 549–552, 1999.        [14] L. Wang et al., “An Energy-Efficient Noise-Tolerant Dynamic Circuit Technique,” IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II, Vol. 47, No. 11, pp. 1300–1306, November 2000.        [15] G. Balamurugan et al., “Energy-Efficient Dynamic Circuit Design in the Presence of Crosstalk Noise,” in Proc. INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN, pp. 24–29, 1999.        [16] G. Balamurugan et al., “The Twin-Transistor Noise-Tolerant Dynamic Circuit Technique,” IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. 36, No. 2, pp. 273–280, February 2001.        [17] F. Murabayashi et al., “2.5 V Novel CMOS Circuit Techniques for a 150 MHz Superscalar RISC Processor,” in Proc. EUROPEAN SOLID-STATE CIRCUITS CONFERENCE, pp. 178–181, 1995.        [18] F. Murabayashi et al., “2.5 V CMOS Circuit Techniques for a 200 MHz Superscalar RISC Processor,” IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. 31, No. 7, pp. 972–980, July 1996.        [19] J. J. Covino, “Dynamic CMOS Circuits with Noise Immunity,” U.S. Pat. No. 5,650,733, July 1997.        [20] D. A. Evans, “Noise-Tolerant Dynamic Circuits,” U.S. Pat. No. 5,793,228, August 1998.        [21] S. Bobba et al., “Design of Dynamic Circuits with Enhanced Noise Tolerance,” in Proc. IEEE INTERNATIONAL ASIC/SOC CONFERENCE, pp. 54–58, 1999.        [22] C. -Y. Wu et al., “Integrated A-Type Differential Negative Resistance MOSFET Device,” IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. SC-14, No. 6, pp. 1094–1101, December 1979.        [23] C. -Y. Wu et al., “The New General Realization Theory of FET-Like Integrated Voltage-Controlled Negative Differential Resistance Devices,” IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, Vol. CAS-28, No. 5, pp. 382–390, May 1981.        [24] L. O. Chua et al., “Bipolar-JFET-MOSFET Negative Resistance Devices,” IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, Vol. CAS-32, No. 1, pp. 46–61, January 1985.        [25] K. K. Ng, “A Survey of Semiconductor Devices,” IEEE TRANSACTIONS ON ELECTRON DEVICES, Vol. 43, No. 10, pp. 1760–1766, October 1996.        [26] L. G. Heller et al., “Cascode Voltage Switch Logic: A Differential CMOS Logic Family,” in Proc. INTERNATIONAL SOLID-STATE CIRCUIT CONFERENCE, pp. 16–17, February 1984.        [27] M. Bhattacharya et al., “Noise Margins of Threshold Logic Gates Containing Resonant Tunneling Diodes,” IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II, Vol. 47, No. 10, pp. 1080–1085, October 2000.        [28] J. P. Sun et al., “Resonant Tunneling Diodes: Models and Properties,” PROCEEDINGS OF THE IEEE, Vol. 86, No. 4, pp. 641–660, April 1998.        [29] P. Mazumder et al., “Digital Circuit Applications of Resonant Tunneling Devices,” PROCEEDINGS OF THE IEEE, Vol. 86, No. 4, pp. 664–686, April 1998.        [30] K. J. Chen et al., “A Novel Ultrafast Functional Device: Resonant Tunneling High Electron Mobility Transistor,” in Proc. IEEE ELECTRON DEVICES MEETING, pp. 60–63, 1996.        [31] J. Stock et al., “A Vertical Resonant Tunneling Transistor for Application in Digital Logic Circuits,” IEEE TRANSACTIONS ON ELECTRON DEVICES, Vol. 48, No. 6, pp. 1028–1032, June 2001.        [32] S. Mohan et al., “Device and Circuit Simulation of Quantum Electronic Devices,” IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, Vol. 14, No. 6, pp. 653–662, June 1995.        [33] S. K. Sunter, “Current-Mirror-Biased Pre-Charged Logic Circuit,” U.S. Pat. No. 4,797,580, January 1989.        [34] J. M. Daga et al., “A Comprehensive Delay Macro Modeling for Submicrometer CMOS Logics,” IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. 34, No. 1, pp. 42–55, January 1999.        
The following U.S. patents are also related to this invention: U.S. Pat. Nos. 4,570,084; 5,065,048; 5,294,566; 5,818,264; 5,903,170; 6,002,292; 6,111,434; 6,130,559, 6,204,696; 6,255,854; 6,323,709; 6,346,831; 6,353,339; and 6,535,041.
Digital integrated circuit noise has become one of the foremost issues in the design of very deep submicron VLSI chips [1]–[2]. Noise in digital integrated circuits refers to any phenomenon that causes the voltage at a node to deviate from its nominal value. While these noises always existed, in the past they had little impact on the performance of integrated circuits and were often neglected. It is the unstopped aggressive technology scaling in an effort to continuously improve chip performance and integration level that makes noise play an increasingly important role in comparison with conventional design metrics like area, speed and power consumption.
Together with technology scaling, aggressive design practices like employing dynamic logic styles have also seen wider use in recent years to achieve higher performance of integrated circuits. Circuits designed using dynamic logic styles can be considerably faster and more compact than their static CMOS counterparts. This is especially the case with wide fan-in dynamic logic gates where a single gate can realize the logic function that otherwise would require multiple-levels of static CMOS logic gates. Therefore, wide fan-in dynamic gates are routinely employed in performance-critical blocks of high-performance chips, such as a microprocessor, digital signal processor, and so on.
Criticism on dynamic circuits is often related to their relatively poor noise tolerance. The switching threshold voltage of a dynamic CMOS logic gate, defined as the input voltage level at which the gate output changes state, is usually the transistor threshold voltage VT. In comparison, the switching threshold voltage of static CMOS logic gate is typically around half the supply voltage. Therefore, dynamic logic gates inherently have less noise immunity than static CMOS logic gates and are the weak link in a high-performance VLSI chip designed using deep submicron process technology.
A number of design techniques have been developed in the past two decades in an effort to reinforce this weak link. For example, feedback keepers were proposed to prevent the dynamic node from floating; internal nodes were precharged to eliminate the charge sharing problem; and weak complementary p-network were constructed to improve the noise tolerance to the level of skewed static CMOS logic gates. However, existing remedial techniques improve dynamic circuit noise tolerance at a significant cost in terms of one or more other important design metrics like circuit area, speed, and power consumption. The fact is that the amount of overhead increases dramatically when the noise tolerance requirement is increased along with the continuous down-scaling of the process technology. Therefore, effective noise-tolerant design techniques that incur little overhead in silicon area, circuit speed and power consumption are highly demanded.
Noise in Dynamic Logic Circuits
A typical n-type domino CMOS logic gate consists of clock controlled transistors M1 and M2, a pull-down n-type transistor network, and an output driver. The operation of a domino CMOS logic gate can be divided into two phases. In the precharge phase when the clock CK is low, the dynamic node S is charged to logic high through M1 and the output of the gate Q is low. The evaluation phase starts when the clock goes high. In this phase, M1 is OFF and M2 is ON. The dynamic node S discharges or retains its charge depending on the inputs to the pull-down network.
Noise sources in dynamic logic circuits can be broadly classified into two basic types: i) gate internal noises, including charge sharing noise, leakage noise, and so on; and ii) external noises, including input noise, power and ground noise, and substrate noise.
Charge sharing noise is caused by charge redistribution between the dynamic node and the internal nodes of the pull-down network. Charge sharing reduces the voltage level at the dynamic node causing potential false switching of a dynamic logic gate.
Leakage noise refers to the possible charge loss in the evaluation phase due to sub-threshold leakage current. Leakage current increases exponentially with respect to transistor threshold voltage, which is continuously being downscaled as the power supply voltage reduces. Therefore, leakage in transistors can be a significant source of noise in wide dynamic logic gates designed using very deep submicron process technology.
Input noise refers to noise presented at the inputs of a logic gate. They are primarily caused by the coupling effect, also known as a crosstalk, among adjacent signal wires. This type of noise has become a prominent source of failures for deep submicron VLSI circuits because of the aggressive interconnect scaling in the lateral dimensions with relatively unchanged vertical dimensions.
Power and ground noise is mainly caused due to the parasitic resistance and inductance at the power and ground networks and at the chip package. Power and ground networks can also be contaminated by external noises from chip pins. Besides obviously reducing gate noise margin due to possibly lowered supply voltage, the power and ground voltage mismatch between a driver gate and a receiver gate can translate to a DC noise at the input of the receiver.
Substrate noise can affect the signal integrity of a logic gate through substrate coupling. Furthermore, since transistor threshold voltage is a function of the substrate voltage, noise in the substrate can momentarily lower the threshold voltage of the transistors in the pull-down network rendering them more susceptible to other noises.
In all, those noises, together with other sources of disturbance like process variation, alpha particle radiation, and so on, can endanger the correct function of dynamic logic circuits designed using very deep submicron process technology. And a desired noise-tolerant design technique should be able to improve the noise immunity of dynamic logic gates against all aforementioned noises.
Overview of Previous Work
In the past two decades, a number of circuit techniques have been developed with a view to improve the noise immunity of dynamic CMOS logic gates. An overview of some significant techniques is described hereinbelow. The techniques are classified into four main categories based on the principle of their operations: 1) using a keeper; 2) precharging internal nodes; 3) raising source voltage; and 4) constructing a complementary p-network.
Employing Keeper
Perhaps the simplest way to enhance the noise tolerance of dynamic CMOS logic gates is to employ a weak transistor, known as keeper, at the dynamic node. The keeper transistor supplies a small amount of current from the power-supply network to the dynamic node of a gate so that the charge stored in the dynamic mode is maintained. In the original domino dynamic logic work [3], the gate of the PMOS keeper is tied to the ground. Therefore, the keeper is always on. Later, feedback keepers (i.e., FIG. 1) became more widely used because they eliminate the potential DC power consumption problem using the always-on keeper in the evaluation phase of domino gates [4].
The use of a keeper causes contention when the pull-down network is ON during the evaluation phase, resulting in slower overall gate performance. In wide fan-in gates designed using very deep submicron process technology, the large leakage current through the n-network necessitates a very strong keeper to retain the voltage at the dynamic node. To reduce the serious contention problem associated with the strong keeper, new keeper design techniques have been recently proposed by Anis et al. in [5]–[6] and Alvandpour et al. in [7]–[8]. Both techniques share the same basic principle, that is, to temporarily disable the keeper during the small time window when the dynamic gate switches. These two techniques have been shown to be very effective in enhancing the noise tolerance of dynamic gates against gate internal noises like leakage noise. However, dynamic gates with those keepers are still susceptible to external noise glitches because the dynamic node is not adequately protected during the gate switching time window.
Referring specifically now to FIG. 1, a typical n-type domino CMOS logic gate, generally indicated at 100, includes a clock-controlled p-type Field-Effect Transistor (FET) 101, a pull-down n-type transistor network 102, and an output driver 103. The operation of the domino CMOS logic gate 100 can be divided into two phases. In the precharge phase when the clock CLK (i.e. 112) is low, the dynamic node 111 is charged to logic high through precharge transistor 101 and the output 110 of the gate 100 is low. The evaluation phase starts when the clock CLK (i.e. 112) goes high. In this phase, the precharge transistor 101 is OFF. The dynamic node 111 discharges or retains its charge depending on the inputs 113 to the pull-down network 102.
A commonly used prior keeper implementation to improve dynamic circuit noise tolerance is included in the circuit 100. This feedback keeper implementation employs a p-type pull-up transistor 120 whose gate terminal is connected to the output 110 of the gate 100. In the precharge phase, gate output node 110 is in the logical 0 state. Therefore, the pull-up transistor 120 is ON which helps to retain the charge at the dynamic node 111. In the evaluation phase, if the pull-down network 102 is not fully ON, the same pull-up current fights against any noise induced lose in charge at the dynamic node 111. If, on the other hand, the pull-down network 102 is fully ON in a regular gate switching operation, the voltage level at the dynamic node 111 decreases and the gate output 110 rises. When the voltage level at gate output 110 is higher than the power supply voltage less the threshold voltage of the pull-up transistor 120, the pull-up transistor 120 is turned off, allowing the dynamic node 111 to be fully discharged to the ground voltage level.
This prior feedback keeper technique is effective against noises and is easy to design. However, there is a fundamental dilemma in choosing the size of the keeper. On one hand, a strong keeper is required to achieve high gate noise tolerance. On the other hand, large keeper leads to significant contention during normal gate switching operation, and therefore deteriorates gate performance.
Precharging Internal Nodes
In complex dynamic logic gates with a large pull-down network, charge sharing between the dynamic node and the internal nodes in the pull-down network often results in false gate switching. A simple yet effective way to prevent the charge sharing problem is to precharge the internal nodes in the pull-down network along with precharging the dynamic node S [9], [10]. When all internal nodes are precharged, this technique is able to eliminate the charge sharing problem at the cost of using a large number of precharge transistors and the increased load capacitance on the clock net. Partial precharge has also been used in design practice as a tradeoff between noise immunity and overheads in chip area and in clock load. NMOS transistors can also be used to precharge the internal nodes if the cost of an inverter to generate the complementary clock signal can be justified. Since the internal nodes are only precharged to VDD−VT, dynamic logic gates using NMOS precharge transistors have reduced discharging time and decreased dynamic power consumption. Finally, it is noted that techniques based on precharging internal nodes alone are not very effective against external noises.
Raising Source Voltage
One effective way to improve noise tolerance against both internal and external noises is to increase the source voltage of the transistors in the pull-down network. Since the gate voltage has to be greater than the sum of the source voltage and the transistor threshold voltage when a transistor is turned on, higher source voltage directly leads to increased gate turn-on voltage. Furthermore, due to the body effect, transistor threshold voltage is increased when the source voltage rises. This also contributes to improving gate turn-on voltage.
The PMOS pull-up advantage [11] employs a PMOS transistor at node N2 forming a resistive voltage divider with the bottom clock-controlled transistor. The voltage at node N2, which determines the switching threshold voltage of the dynamic logic gate, can be adjusted by changing the relative size of the PMOS pull-up transistor. One major drawback of this technique is the DC power consumption in the resistive voltage divider. Furthermore, since the voltage level at the dynamic node S can never get lower than the voltage at node N2, the voltage swing at node S is not rail-to-rail. When the size of the PMOS pull-up transistor is large in an effort to aggressively raise gate noise immunity, the gate output may also not have a rail-to-rail swing.
An improved method employs a pull-up transistor with feedback control [12]. Here, an NMOS transistor M1 is used to pull up the voltage of an internal node. The gate of the pull-up transistor is connected to the dynamic node of the domino gate. This design allows the pull-up transistor to be shut off when the voltage of the dynamic node goes low, therefore, the dynamic node S undergoes rail-to-rail voltage swing. Also, the DC power consumption problem is partially solved. It occurs only under certain input combinations that do not turn on the pull-down network. A PMOS transistor can similarly be used in this technique provided that the gate of the PMOS transistor is connected to the output of the dynamic logic gate.
The mirror technique [13], [14] employs a feedback-controlled NMOS transistor similar to the NMOS pull-up technique. In addition, it duplicates the pull-down network in an effort to further reduce DC power consumption and to further improve gate noise tolerance. Whenever the pull-down network is OFF, the mirror network is also OFF, hence, cutting off the potential DC conducting path from the NMOS pull-up transistor through the bottom clock-controlled transistor. Therefore, the DC power consumption problem is completely solved. However, this technique significantly lengthens the discharge path in the pull-down network, which potentially leads to slower circuit or considerably increased circuit active area when the transistors are aggressively sized.
The twin transistor technique [15], [16] adopts NMOS pull-up transistors at all internal nodes to further improve dynamic gate noise immunity. In addition, the drain nodes of the pull-up NMOS transistors are connected to the inputs instead of to the power supply network. By doing so, unnecessary injection of current by the pull-up transistors is avoided, resulting in lower gate power consumption. However, this technique leads to increased gate input capacitance which may slow down the switching of the gates in the previous stage. Further, this technique is not suitable for certain logic functions because it may short input nodes.
Constructing Complementary p-Network
The basic principle of this class of techniques is to construct a weak complementary p-network to prevent the dynamic node from floating in the evaluation phase. In one such technique [17], [18], a gate operates in a similar way as a normal domino gate in the precharge phase. In the evaluation phase, the logic gate behaves as a skewed CMOS logic gate. Therefore, the switching threshold voltage of the dynamic logic gate is equivalent to that of a skewed CMOS logic gate. In addition to the silicon area overhead associated with the pull-up network, a major drawback of this technique in practice is its ineffectiveness in dealing with very wide logic gates, for example, wide OR gates, where dynamic logic styles really outshine static CMOS logic gates in performance.
PMOS transistors can also be employed at a per transistor level. This technique is known as CMOS inverter technique [19]. The relative size of the PMOS transistors can be varied to adjust the switching threshold of the dynamic logic gate. One advantage of this technique is that it can be selectively applied to a subset of inputs if they can be identified as noisy in advance. The main drawback of this technique is that it is not suitable for OR type logic gates because of possible serious DC currents under certain input combinations. The simple 3-input OR-AND gate will be used as an example. When inputs A and C are high and input B is low, there is a direct conducting path between the power supply network and the ground node. More hazardous than the obvious problem of DC power consumption, the voltage at node S is determined by the relative strength of the pull-up transistor M2 and that of the transistors in the discharge path. The gate may fail to switch when the pull-up transistor is sized relatively strong in an effort to aggressively improve gate noise tolerance.
The dynamic node can be false reset with certain input combinations using either of the two above techniques. With a view to solve this false reset problem, Evans in [20] used an additional transistor M3. M3 is ON when the gate output remains low. When the evaluation is executed and the output rises, M3 is turned OFF disconnecting the pull-up transistors from the power supply network. Similar tactic can also be applied to improve the simple complementary p-network technique. This gated CMOS inverter technique does not completely solve the DC conducting problem for certain logic circuits.
A noise-tolerant 2-input AND gate using a triple transistor technique has been provided [21], where each NMOS transistor in the pull-down network of a simple dynamic logic gate is replaced by three transistors. The technique can be considered as a variation of the CMOS inverter technique where an additional NMOS transistor is used to prevent the possible DC conducting path problem in the evaluation phase. Similar to the mirror technique, this technique significantly lengthens discharge paths in the pull-down network. While it can be useful for certain logic gates like wide-OR gates, it is not practical to be applied to general pull-down NMOS network because of its overhead in circuit area and performance.
Comparison of Techniques
In this subsection, the noise-tolerant design techniques described in the previous subsections are compared. A listing of the set of basic requirements that a desirable noise-tolerant design technique should meet is as follows:                1. It improves gate noise tolerance against all types of noises.        2. It is suitable for all logic functions.        3. It has minimal circuit area overhead.        4. It has minimal circuit speed overhead.        5. It consumes no DC power and has minimal AC power consumption overhead.        
Dynamic circuit noise enhancing techniques discussed in this section are compared in Table 1. The first three columns are self-explanatory. The fourth column is the approximate number of transistors needed in a large dynamic logic gate, where N is the number of transistors in the pull-down network of the original dynamic logic gate. The fifth and sixth columns indicate whether the input load capacitance and clock load capacitance are unchanged when a noise-tolerant design technique is used. The seventh column shows whether the length of the discharge paths in the pull-down network is intact. The eighth column indicates whether the dynamic gate maintains the zero DC power consumption property. The ninth column shows whether the technique enhances noise tolerance against both internal and external noises. And finally, the last column shows whether the technique can be applied to all logic gates.
It is shown in the table that the twin transistor technique and CMOS inverter based techniques are not suitable for all logic functions. Techniques based on precharging internal nodes as well as the two new feedback keeper techniques only improve gate noise immunity against certain types of noises. Both the PMOS pull-up technique and the NMOS pull-up (with feedback) technique consumes DC power. The mirror technique and the triple transistor technique increase the length of gate discharge path. Techniques based on raising source voltage usually either have DC power consumption or require significantly larger silicon area. Techniques based on constructing complementary p-network often require larger silicon area and they increase the previous stage gate delay due to greater gate input capacitance.
In all, simple feedback keeper is the only general purpose technique that improve dynamic logic gate noise immunity against all types of noise without significant increase in silicon area (device count), speed, and power consumption.
TABLE 1Comparison of Existing Dynamic Circuit Noise Tolerance Enhancing TechniquesNum.InputClockDischrgDCAllAllClassTechniqueRef.tran.loadaloadaPathacurrentanoisesaFuncaAAlways-on keeper[3]N∘∘∘x∘∘Feedback keeper[4]N∘∘∘∘∘∘HS feedback keeper[5]N∘∘∘∘x∘Conditional feedback[7]N∘∘∘∘x∘keeperBPrecharge internal[9]2N∘x∘∘x∘nodesPartial precharge[10]N∘x∘∘x∘CPMOS pull-up[11]N∘∘∘x∘∘NMOS pull-up[12]N∘∘∘x∘∘(feedback)Mirror technique[13]2Nx∘x∘∘∘Twin transistor[15]2Nx∘∘∘∘xDComplementary[17]2Nx∘∘∘∘∘p-networkCMOS inverter[19]2Nx∘∘∘∘xGated CMOS[20]2Nx∘∘∘∘xinverterTriple transistor[21]3Nx∘x∘∘∘aSymbol ∘ represents “good” and symbol x represents “not good.”